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Analog - TimingPLL
PLL - 320MHz, 50ps peak-peak jitter, 25uA IDD PLL - Integer N / Fractional N and delta sigma for GPS, DBM and WCDMA Wideband amplifier - low noise buffer - 40MHz sinusoidal clock output PLL - CP, PFD, Loop Filter, divider, logic & calibration - 44MHz/160MHz Integer N PLL - 44MHz integer N with ring osc for micro clocking Digital calibration circuits for analog PLL PLL - PFD, charge pump, loop filter, divider, calibration <1MHz Oscillator
VCO
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